Powering a precision SAR ADC with an efficient, ultra-low power switcher

April 14, 2016 // By Alan Walsh
AD7980 and ADP5300 application circuit
Alan Walsh explains how to power a precision SAR ADC with an efficient, ultra-low power switcher.

Precision measurement is extending into application areas that require greater and greater power efficiency. This is particularly true with the advent of IoT which is driving greater need for wireless sensor nodes with precision measurement capability, battery powered wearable fitness/medical devices and industrial signal chains that use isolated power, 4-20 ma loop powered or battery powered field instruments. In these scenarios greater power efficiency means longer battery lives with less maintenance as well as simplified power supply design.

Typically precision measurement systems use low-dropout regulators (LDOs) as part of their power supply schemes to generate low noise rails for precision ADCs. However LDOs can be very inefficient in delivering power and often the majority of power is lost in the LDO dissipated as heat. This article discusses a means of achieving a higher efficiency power solution for your precision successive approximation register (SAR) ADC. This is achieved  by use of a ultra-low power switching regulator in a hysteretic mode and analyzing the performance trade-offs including a means to intelligently control the switching regulator synchronous to the SAR conversion to improve noise performance.

Fixed frequency or pulse-width modulated (PWM) switching regulators provide a very efficient (often > 90%) means of generating voltage rails in a measurement system at medium to high load currents (100 mA’s to A’s). However this efficiency comes at the cost of switching ripple that is usually at a fixed frequency of 100’s kHz to a couple of MHz. As can be seen in Figure 1 the power supply rejection ratio, or PSRR, of a typical precision SAR ADC is very good at lower frequencies up to ~100 kHz, beyond this the PSRR drops off rapidly.

Figure 1: SAR ADC Analog Power supply rejection versus frequency

This means that the ripple from fixed frequency or PWM switchers is not very well rejected and shows up at the ADC digital output. This can usually be seen in an FFT

Design category: