An unconditionally stable loop for voltage-mode-controlled synchronous-buck converters
Design of voltage-mode controlled synchronous buck converter can result to a conditionally stable loop using conventional compensation design methods. In such cases, the compensator provides the desired loop bandwidth with good stability margin at nominal operating point while load transient response indicates a robust performance of the converter.
However, the control loop becomes unstable at certain conditions such as the drop of input voltage. To avoid these undesired situations, the compensation network is usually modified to achieve unconditional stability.
The demand for wide-input-voltage, high-frequency non-isolated synchronous-buck converter has rapidly increased in recent years. It is desired to design wide control-loop bandwidth for this converter to benefit the high-frequency operation and minimize the number of output capacitors.
However, it is possible a wide loop-bandwidth design to be conditionally stable. Even though the problem of conditionally stable converters is not new among power-electronics engineers, it can be ignored during application development and evaluation since common stability metrics such as phase margin and load transient response at nominal condition do not reveal it.
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About the authors
Peyman Asadi is a Staff System/Application Engineer at International Rectifier, where he is responsible for defining and developing of power management products for point-of-load (POL) applications. His interests include control and design of high-frequency DC/DC converters. He received a Ph.D. (2006) in electrical engineering from Texas A&M University, College Station, TX.
Amir Rahimi received the B.S. and M.S. degrees in electrical engineering from Sharif University of Technology, Tehran, Iran, in 1999 and 2001, respectively, and the Ph.D. degree in electrical engineering from the Illinois Institute of Technology, Chicago, in 2008.
He is currently a Senior System/Application Engineer at International Rectifier, Irvine, CA, where he is responsible for defining and developing new low-voltage switching-regulator ICs for point-of-load applications.
Parviz Parto is Director of Systems Applications Engineering at International Rectifier. He has more than 15 years design experience in power electronics. He received his M.S. from Chalmers University of Technology, Gothenburg, Sweden in electrical engineering. He is author or coauthor of many technical papers and holds U.S patents in area of power management.
His interests include high-frequency switching-mode power supplies and ICs for power-management applications. He is responsible for defining and developing power-management products for point-of-load applications.
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