Cadence accelerates giga-scale 20nm design with next-generation Encounter RTL-to-GDSII Flow release
The new RTL-to-GDSII flow further advances Cadence’s technology in power, performance, and area for the world’s most advanced high-performance, low-power SoC designs. The flow is enabled by Encounter RTL Compiler, Encounter Test, Encounter ECO Designer, Encounter Digital Implementation System, Clock Concurrent Optimization (CCOpt), Encounter Timing System, Encounter Power System, Cadence QRC Extraction, Cadence Physical Verification System, and design for manufacturing technologies.
The new Encounter 20-nm methodology delivers silicon-proven 20-nm capabilities with correct-by-construction double-patterning support, covering capabilities from floorplanning, placement and routing to signoff timing, power and physical verification. The approach improves die area efficiency of 20-nm double-patterning designs, and enables more efficient engineering change order (ECO) revisions. Enhancements to the Cadence Physical Verification System provide foundry-qualified 20-nm in-design checking and final signoff verification to ensure DRC and double patterning color correctness.
The latest release of the Encounter RTL-to-GDSII flow also includes the new GigaOpt engine, which integrates key physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a highly scalable optimization engine that supports designs featuring leading high-performance processors. By harnessing the power of multiple CPUs, the engine produces results much faster than traditional optimization engines. In addition, the new differentiated CCOpt technology unifies clock tree synthesis with physical optimization, resulting in up to 10 percent improvement in design performance, and up to 30 percent reduction in clock tree power and area.
Another key element of the release is GigaFlex technology, a new capability that expands the capacity to handle today’s largest designs of 100 million instances or more . Designers can now achieve full-chip design prototyping goals in just 10 percent of the time required previously, enabling them to uncover potential issues earlier to produce the optimal design floorplan sooner. The GigaFlex technology enables concurrent top-and-block hierarchical design and implementation, reducing iterations and total design cycle time by an order of magnitude. In addition, automated functional ECO technologies accelerate pre- and post-mask ECO changes, which are reduced to hours or days through smart hierarchical design handling.
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