Power Tip 44: Handling high dI/dt load transients, Part 1
With many central processing units (CPUs), specifications require that the power supply must be capable of providing large, rapidly changing output currents, typically as the processor changes operating modes.
For instance, in a 1-volt system, the requirement may be to stabilize the supply voltage within three percent for a 100 A/µsec load transient. The key to attacking this problem is to realize that this is not just a power supply problem but a power distribution system problem as well, and the two become intertwined in the solution.
The implication of these high di/dt requirements is that the voltage source must have very low inductance. Rearranging the following expression and solving for the allowable source inductance:
There can be only 0.3 nH of inductance in the path of the rapid load-current transient. For comparison, the inductance of a 0.1 inch-wide (0.25 cm) circuit-board trace on a four-layer board has an inductance of about 0.7 nH/inch (0.3 nH/cm). The typical inductance of a wire bond within an IC package is in the 1 nH range, and vias in a printed circuit board are in the 0.2 nH range.
There also is a series inductance associated with bypass capacitors as illustrated in Figure 1. The top curve is the impedance of a single 22 µF, X5R, 16V, 1210 ceramic capacitor mounted on a four-layer circuit board.
Figure 1: Parasitics in parallel capacitors impedance
(Click here for enlarged image)
As expected, below 100 kHz, the impedance drops with increasing frequency. However, there is a series resonance at 800 kHz where the capacitor begins to turn inductive. The inductance, which can be calculated from the value of the capacitor and the resonant frequency, is equal to 1.7 nH which is well above our goal of 0.3 nH. Luckily, you can parallel capacitors to reduce the effective ESL.
The bottom curve in Figure 1 is the impedance of two parallel capacitors showing a reduction in impedance. One interesting thing is that the resonance has shifted slightly lower, which indicates that the effective inductance is not exactly one half. Based on the resonant frequency, the new inductance is 1.0 nH or a 40 percent reduction in the ESL for two inductors in paralle, rather than an expected 50-percent drop. This effect can be attributed to two causes: an interconnect inductance, and a mutual inductance between the two capacitors. .
The loop size of the current path determines the parasitic inductance in connecting components and to a degree, the size of the components determines the loop area. This size-to-inductance correlation is evident in Table 1 which shows capacitor inductance for various sizes of ceramic surface mount capacitors.
Table 1: Ceramic SMT capacitor size affects parasitic inductance
Generally, physically larger capacitors have larger inductances. This table does not include the effects of mounting capacitors on a circuit board, which in our previous measurements increased the inductance from 1 nH to 1.7 nH.
Another interesting point is the location of the terminations has a significant impact on inductance. The 0805 capacitor has terminations on the shorter side of the capacitor while the 0508 capacitor has them on the longer side. This cuts the current path nearly in half and also broadens it, resulting in significantly reduced inductance. This alternate configuration provides a four-to-one reduction in inductance.
To summarize: High di/dt loads require careful bypassing to preserve power supply dynamic regulation. Surface mount capacitors need to be mounted extremely close to the load to minimize their interconnect inductance. Capacitors have parasitic inductance that may prevent adequate decoupling.
Paralleling capacitors to reduce this parasitic inductance is effective, but interconnect and mutual inductance diminishes the impact. Using capacitors with shorter current paths is also effective. This can be accomplished with physically smaller parts, or parts with alternate terminations which use the shorter dimension for current flow.
In a forthcoming article we will continue our discussion on high di/dt transient loads and their implications in designing and testing suitable power supplies. We will move from the local bypass to implications on the power supply.
For more information about this and other power solutions, visit: www.ti.com/power-ca.About the author
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