Developing an ultra high intercept last gain stage to a 14-bit high SFDR ADC (Part 1 of 2)
June 18, 2012 | Michael Steffes and Jian Wang | 222904743
Part 1 of this series will describe the individual ADC and amplifier characteristics, show a proposed 19dB gain interface circuit including a 2nd order RLC filter between the amplifier and ADC.One common RF receiver chain mixes down to a 70MHz center frequency using low cost SAW filters to define the bandwidth out of the last mixer. This relatively low signal level SAW filter output must then be raised up to be a large part of an ADC input range for digitization. It would be desirable to provide this last gain stage with very low 3rd order intermodulation (IM3) spurious to keep closely spaced carriers from creating false signals on top of desired signals in the final FFT.
While ADCs have continued to improve in their IM3 characteristics, systems of this type have often depended on relatively high power RF amps (>500mW) to provide adequate IM3 in this last stage. Recent amplifier advances have opened a path to very low power solutions where the amplifier IM3 is well below the mid -80dBc to -90dBc performance found in emerging low power ADCs.
If the IM3 is acceptable, to complete the system design, it would be desirable to include a low order bandpass filter to limit the wideband noise and other distortion terms that might be added by this last stage. While the IM3 tones are often very close to the desired signals and will get no filtering, the IM2 and simple harmonic terms can be far away from the desired bandpass edges and perhaps only modest filtering is required.
Part 2 of the series will describe some simple circuit changes to improve the single tone results and then show tested 2-tone Intermodulation (IM3) performance. Making these super low IM3 measurements (-110dBc for the amplifier itself) can benefit from some extra effort on the input signal and those approaches will be described in detail. Read part 1 here.
Michael Steffes is Sr. Applications Manager and Jian Wang is Lead Applications Engineer in the High Speed Signal Path Products at Intersil Corp.
Please login to post your comment - click here
- No news
MOST POPULAR NEWS
- Volvo evaluates flywheel hybrid drive - fuel savings of up to 25%
- PV storage market is set to grow to USD19bn by 2017
- Ultra-low-power SoC supports world's smallest Bluetooth location stickers
- Power-One enters into patent license agreement with Microchip
- Quad-MOSFET solution boosts efficiency and eliminates heat sinking in active bridge applications
- Solar industry capital spending hits seven-year low in 2013 but upturn is on the cards
- Market for GaN and SiC power semiconductors set to rise by factor of 18 in next decade
- Imec and Renesas collaborate on ultra-low power short range radios
- Advanced microcontroller combines floating point and low leakage technology to achieve longest battery lifetime in portable applications
- World's lowest power Bluetooth smart chip is unveiled
- Dangers of Aftermarket Counterfeit Battery Packs
- High Voltage Surge Stoppers Ensure Reliable Operation During Power Surges
- Motor-Drive Design made Simple
- Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications
- Micropower Isolated Flyback Converter with Input Voltage Range from 6V to 100V
- Derating of Schottky Diodes
- Heatsink Optimization
- High Performance ZVS Buck Regulator Removes Barriers To Increased Power Throughput
- Waste heat replaces batteries
- Stepper Motor Control IC