Technology News
First samples of low cost, low power LatticeECP4 FPGAs start shipping
June 07, 2012 | Paul Buckley | 222904701
Lattice Semiconductor Corporation has begun shipping the highest density member of the company’s next generation LatticeECP4 FPGA family to select customers.
The new LatticeECP4 FPGA family offers the richest portfolio of low cost, low power mid-range devices under 200K LUTs, with high performance innovations such as 6G SERDES in low cost packages, powerful DSP blocks and built-in hard IP-based communication blocks.
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing (DSP) blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro basestations, small cell stations, pico stations, microwave and millimeter-wave backhaul links.
The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
"With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the device’s low power and economy," said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. “The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.”
Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. Lattice Diamond design software is the flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enable designers to more quickly target low power, cost-sensitive FPGA applications. In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include an accurate power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.
The LatticeECP4 FPGA family features low cost, low power mid-range devices with numerous high performance innovations. The family offers standards-compliant multi-protocol 6G SERDES in low cost wire-bond and flip-chip packages, DDR1/2/3 memory interfaces with speeds up to 1066 Mbps and powerful, cascadable DSP blocks that are ideal for high performance RF, baseband and image signal processing. The LatticeECP4 claims to be the only FPGA family with high throughput, double data rate DSP blocks and up to 36 embedded clock and data recovery (CDR) circuits. The embedded CDRs can be combined with general purpose I/Os (1.25 Gbps LVDS) to implement a large number of serial Gigabit interfaces. The LatticeECP4 FPGAs also feature embedded memory of up to 5.9 Mbits. Logic density varies from 30K LUTs to 190K LUTs with up to 456 user I/O. The LatticeECP4 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure, wireline access equipment, video, imaging and computing applications.
Availability and Pricing
The LatticeECP4-190 silicon and Lattice Diamond 2.0 beta software have been released to select customers developing market-leading solutions. Prices for the LatticeECP4-190 device in the 676fcBGA package in 100K unit volumes will start at $60 for delivery in the second half of 2013.
More information about the LatticeECP4 FPGA family at
www.latticesemi.com/ecp4
The highest density device in the family, the LatticeECP4-190, features 183K LUTs, 480 double data rate DSP multipliers (18x18), 5.8 Mbits of memory and twelve 6 Gbps SERDES channels, making it ideally suited for a broad range of cost- and power-sensitive wireless, wireline, video and computing applications. Lattice has released three flip-chip packages for the LatticeECP4-190 (676, 900 and 1152 pins) that are well suited for a wide range of applications.
The LatticeECP4-190 FPGA offers high-speed CPRI and SRIO 2.1 interfaces and double data rate digital signal processing (DSP) blocks for building heterogeneous wireless networks. The LatticeECP4 FPGAs facilitate rapid construction of the latest 3G/4G metro basestations, small cell stations, pico stations, microwave and millimeter-wave backhaul links.
The LatticeECP4-190 FPGA also provides wireline access developers with 36 embedded clock and data recovery (CDR) circuits to build high port density switches and routers using innovative low cost, low power FPGAs. The DSP blocks and a growing portfolio of third-party intellectual property cores and reference designs are also enabling video and surveillance camera customers to implement complex algorithms using affordable, mid-range FPGAs.
"With the silicon release of our LatticeECP4-190 devices, our customers can implement even more complex designs for wireless base stations and backhaul, wireline access, video and display applications and still benefit from the device’s low power and economy," said Sean Riley, Lattice Corporate Vice President and General Manager, Infrastructure Business Unit. “The next generation LatticeECP4 FPGA family brings premium features to infrastructure customers while maintaining industry-leading low power and low cost.”
Select customers have early access to Lattice Diamond 2.0 beta design software and can begin to design and program their new samples immediately. Lattice Diamond design software is the flagship design environment for Lattice FPGA products and provides a complete set of powerful tools, efficient design flows and a user interface that enable designers to more quickly target low power, cost-sensitive FPGA applications. In addition, Lattice Diamond software continues to provide industry-leading features specifically developed for low cost and low power applications. These include an accurate power calculator, a pin-based simultaneous switching output noise calculator and proven MAP and PAR FPGA implementation algorithms that help ensure low cost and low power design solutions.
The LatticeECP4 FPGA family features low cost, low power mid-range devices with numerous high performance innovations. The family offers standards-compliant multi-protocol 6G SERDES in low cost wire-bond and flip-chip packages, DDR1/2/3 memory interfaces with speeds up to 1066 Mbps and powerful, cascadable DSP blocks that are ideal for high performance RF, baseband and image signal processing. The LatticeECP4 claims to be the only FPGA family with high throughput, double data rate DSP blocks and up to 36 embedded clock and data recovery (CDR) circuits. The embedded CDRs can be combined with general purpose I/Os (1.25 Gbps LVDS) to implement a large number of serial Gigabit interfaces. The LatticeECP4 FPGAs also feature embedded memory of up to 5.9 Mbits. Logic density varies from 30K LUTs to 190K LUTs with up to 456 user I/O. The LatticeECP4 FPGA family is ideally suited for deployment in high volume cost- and power-sensitive wireless infrastructure, wireline access equipment, video, imaging and computing applications.
Availability and Pricing
The LatticeECP4-190 silicon and Lattice Diamond 2.0 beta software have been released to select customers developing market-leading solutions. Prices for the LatticeECP4-190 device in the 676fcBGA package in 100K unit volumes will start at $60 for delivery in the second half of 2013.
More information about the LatticeECP4 FPGA family at
www.latticesemi.com/ecp4
Please login to post your comment - click here
Related News
- Nujira surpasses own world record for ET PA linearity
- Silica moves to fast lane in Europe's LED market
- PCIe clock generators offer the smallest footprint and lowest power
- 60-V integrated power modules extends power capability of low load-impedance Class D audio systems
- PFC IC enables compact designs for consumer products and PCs
- Radiation hardened DC-DC power conversion devices support space power systems
- 650-V n-channel power MOSFET series adds 23 new high power density devices
- LED power supply suits hand-held devices
- Integrated PFC IC for compact consumer products
- 420-W quarter brick DC-DC converters are PMBus compliant
MOST POPULAR NEWS
- Volvo evaluates flywheel hybrid drive - fuel savings of up to 25%
- PV storage market is set to grow to USD19bn by 2017
- Ultra-low-power SoC supports world's smallest Bluetooth location stickers
- Power-One enters into patent license agreement with Microchip
- Quad-MOSFET solution boosts efficiency and eliminates heat sinking in active bridge applications
- Imec and Renesas collaborate on ultra-low power short range radios
- Solar industry capital spending hits seven-year low in 2013 but upturn is on the cards
- Market for GaN and SiC power semiconductors set to rise by factor of 18 in next decade
- Advanced microcontroller combines floating point and low leakage technology to achieve longest battery lifetime in portable applications
- World's lowest power Bluetooth smart chip is unveiled
Interview
Technical papers
- Dangers of Aftermarket Counterfeit Battery Packs
- High Voltage Surge Stoppers Ensure Reliable Operation During Power Surges
- Motor-Drive Design made Simple
- Adaptive Cell Converter Topology Enables Constant Efficiency in PFC Applications
- Micropower Isolated Flyback Converter with Input Voltage Range from 6V to 100V
- Derating of Schottky Diodes
- Heatsink Optimization
- High Performance ZVS Buck Regulator Removes Barriers To Increased Power Throughput
- Waste heat replaces batteries
- Stepper Motor Control IC
Poll
Microcontrollers
Batteries
Power
Energy Harvesting
IMS Research
Diodes
NXP Semiconductors
Photovoltaic
MOSFETs
Solar
GaN
Power Supply
Power Management
International Rectifier
Fairchild Semiconductor
MOSFET
Texas Instruments
Battery
Linear Technology
Intersil
Smart Grid
Maxim Integrated Products
UPS
STMicroelectronics
Analog
Microcontroller
Analog Devices
Vishay Intertechnology
National Semiconductor
Power Supplies
All material on this site Copyright © 2009 - 2010 European Business Press SA. All rights reserved.
This site contains articles under license from EETimes Group , a division of United Business Media LLC.
This site contains articles under license from EETimes Group , a division of United Business Media LLC.


