The Layerscape architecture is a fundamental new approach to networking system architectures and includes a family of multicore ARM Cortex (above) and Power Architecture devices.

The architecture modularizes packet acceleration and forwarding operations from high-level routing decisions; streamlines interaction between the layers; leverages a synchronous run-to-completion model; and supports a consistent programming framework across the architecture using standard C/C++ languages. The extreme programming flexibility and scale of the architecture enable real-time, ‘soft’ control over the network, preserve software investments and help to ensure continued evolution.

“To address the need for more intelligent, dynamic networks, Freescale has taken our QorIQ platform a significant step further with the new software-aware Layerscape architecture,” said Tom Deitrich, senior vice president and general manager of Freescale’s Networking & Multimedia Solutions Group. “We’ve made software awareness an integral part of our new architecture instead of an afterthought. With innovations including core-agnostic compatibility, independent, highly efficient packet processing and real-time visualization capability, we’re accelerating the network’s IQ.”

The architecture is the foundation of a broad array of forthcoming QorIQ multicore processors, from many-core data path devices delivering up to 100 Gbps of performance to highly integrated, cost- and energy-efficient products operating at less than 3 W, using both Power Architecture and ARM technologies as appropriate.

The modular Layerscape architecture consists of three independent, scalable layers, allowing Freescale to design QorIQ devices with expanded, reduced or removed layers as needed, providing the optimal solution for a given application. The first of three layers is a General-Purpose Processing Layer (GPPL) for general purpose compute performance. This layer is optimized for virtualized cloud services and control plane applications. The Accelerated Packet Processing Layer (APPL) performs autonomous packet processing and enables customers to program value-added capabilities in a sequential, synchronous, run-to-completion model that abstracts the hardware microarchitecture and gives customers an embedded, C-based programming model. The third, Express Packet I/O Layer (EPIL), provides deterministic wire-rate performance between network interfaces up to 100G, supporting switching capabilities for L2 and above.

Layerscape also provides developer technologies that help customers efficiently deploy, configure, tune and manage systems. This includes support for open-standard software programming models such as software-defined networks (SDNs), as well as a system profiling and visualization tool that allows for detailed scenario analysis and streamlines development processes. A platform-independent API for user space application programming called the VortiQa Platform Services Package (PSP) is designed to simplify application migration. This abstracts hardware complexity, enables application development within the familiar Linux user space and enables standard C programming. Internal Freescale support includes the CodeWarrior integrated development environment (IDE), as well as reference design boards, advanced compliers, CodeWarrior debug and configuration tools, models and the QorIQ optimization suite.

The first two QorIQ product families based on the Layerscape architecture are the LS-1 and LS-2 dual core ARM devices. These include virtualization support, advanced security, an array of advanced interconnects, a common ISA and software- and pin-compatibility for simple and smooth application migration between the two families. The outstanding performance-per-watt and advanced integration of the LS-1 and LS-2 product families open the QorIQ portfolio to additional markets, including applications with novel form factors and entirely new product categories.

The LS-1 family (above) features two ARM Cortex-A7 cores running at up to 1.2 GHz with one of the highest levels of integration ever offered in a sub-3-W embedded processor. The LS-2 family features two ARM Cortex-A15 cores running at up to 1.5 GHz and under 5 W total power. Targeted applications for the LS-1 and LS-2 families include residential gateways, enterprise access points, smart energy systems, industrial communications, line cards and robotics.

Future QorIQ processors based on the Layerscape architecture will leverage Power Architecture technology using the e6500 core, which will be among the highest-performance cores featured in the new portfolio.

Initial samples of the first products based on the Layerscape architecture are expected in mid-2013.

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