Guidelines For Supplying Power to High Speed ADCs
December 13, 2010 | Michael Cobb | 222901922
Michael Cobb, Applications Engineer, High-speed Signal Processing Group, Analog Devices, provides background on ADC power domains and sensitivities and addresses basic guidelines for supplying power to high speed ADCs.In order to get maximum performance from a high speed analog to digital converter it must be supplied with clean DC power supplies. A noisy power supply can lead to lowered SNR and/or undesired spurious content in the ADCs output.
Analog and Digital Supplies
Most of today’s high speed analog to digital converters have at least two supply domains, an analog supply (AVDD) and a digital and output driver supply (DRVDD). Some converters have an additional analog supply which typically should be treated like an extra AVDD supply discussed here. The analog and digital supplies on a converter are separated in order to prevent the digital switching noise (particularly the noise generated from the output drivers) from interfering with the sampling and processing of the analog sample on the analog side of the part. Depending on the signal being sampled this digital output switching noise can have significant frequency content and can easily degrade both noise and spurious performance if this noise is allowed back into the analog or clock inputs of the part or into the analog side of the chip through the power supplies.
For most high speed analog to digital converters two separate supplies are recommended for AVDD and DRVDD. These two supplies require sufficient isolation to prevent any digital switching noise on the DRVDD supply from reaching the AVDD supply of the converter. Often separate regulators are used for the AVDD and DRVDD supplies, however, if sufficient filtering between the two supplies is implemented it is usually possible to get adequate performance from one source.
ADC power supply sensitivity - PSRR
One method to determine a high speed ADCs sensitivity to power supply noise is to examine its power supply rejection by imposing a known frequency on the converter’s power supply rail and looking at the resulting tone appearing in the converter’s output spectrum. Looking at the relative power of the input signal versus the signal appearing in the spectrum determines the converter’s power supply rejection ratio (PSRR) at a given frequency. The plot below shows PSRR versus frequency for a typical high speed ADC. The data in this plot was taken with the part mounted on an evaluation board with bypass capacitors installed – this method shows how the part responds to power supply noise in a typical application. Note that in this case the converter’s PSRR is much higher at low frequencies and drops significantly above about 10MHz.
Figure 1: Typical ADC Power Supply Rejection versus Frequency
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This PSRR information allows a designer to determine the level of ripple allowable on the power supply to prevent this noise from disrupting the converter’s performance. For instance if a supply has 5 mV p-p ripple at 500 kHz the converter from the PSRR plot below would provide about 58dB of rejection at this frequency. So with the converter’s full scale at 2Vp-p the original 5mV signal is 52 dB below the input full scale so the this signal would be attenuated by an additional 58 dB to 110 dB below the full scale power of the converter. In this way a designer can use the converter’s PSRR data to determine the allowable ripple at a given frequency on the converter’s power supply. So if the converter’s supply has ripple at a known frequency, such as from an upstream switching converter, this method can be used to determine the additional filtering necessary to attenuate this noise to an acceptable level.
This analysis assumes only one frequency is present on a given power supply. Depending on how the supply is derived and what other devices are powered from the supply, the noise on a supply can have additional frequency content. If this is the case a designer must ensure that adequate filtering is provided on the supply to attenuate this noise. Remember that noise outside the ADC’s input band of interest in other Nyquist zones can get folded into the band of interest due to the wideband nature of the ADC input.
Linear Regulator Discussion
Traditionally, linear regulators have been utilized to provide clean power to the AVDD and DRVDD rails of a converter. Low dropout linear regulators provide excellent rejection of low frequency noise up to about 1MHz. The control loop bandwidth of a typical LDO runs out at this frequency and higher frequencies are passed through the regulator with little attenuation. For noise above this frequency additional filtering must be employed after the LDO to provide attenuation to prevent this noise from reaching the ADC. Typically a combination of ferrite beads, bulk decoupling, and local supply decoupling is adequate to attenuate any high frequency noise that gets through the linear regulator. When designing power supply filters care must be taken when using series inductive components to ensure that inductive ‘kicks’ at power up and power down don’t reach levels high enough to cause damage to the converter.
Figure 2: LDO Powered ADC Including Filtering
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Also, since a switching converter is often found upstream from the LDO a designer must ensure that the frequency of the switcher is adequately suppressed by the LDO/filter circuit. Modern switching converters are moving to higher and higher switching frequencies which can be higher than the loop bandwidth of a typical LDO. Noise from these higher frequency switchers can easily pass through the LDO and must be attenuated with downstream filters.
While the linear regulators do an excellent job of supplying clean power to an ADC, their primary disadvantage is their efficiency. Depending on the voltage supplied to the input of the linear regulator the efficiency of an LDO can be very low. Improving this efficiency by supplying a voltage just above the LDO’s dropout voltage often results in adding extra supply stages which add cost and complexity to a power supply design.
Switching Regulator Discussion
Historically, switching regulators have not been recommended for directly powering ADCs. However, today’s switching regulator technology, when combined with post-switcher filtering and careful design and layout practices, allows these regulators to be employed as a more efficient power solution for many high speed analog to digital converters. As shown in Figure 2 switching regulators can provide up to 95% efficiency, providing a significant reduction in system power consumption over LDOs. For a single 1.8 V ADC consuming 780 mW, use of switching regulator power supply can save 640 mW or more from the overall system power consumption. Since switching power supply designs eliminate the linear stages which dissipate heat, overall heat generation on a PCB is lower potentially reducing the need for extra cooling measures such as fans and heatsinks.
Figure 3: Typical Efficiency of a Switching Regulator
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Switching regulators do, however, generate noise which must be controlled through careful design and layout practices. Switching power supplies produce two main types of noise: switching ripple and high-frequency noise. For constant-frequency switchers, switching ripple generates energy at the switching frequency and its multiples. High-frequency noise is generated by the rapid voltage and current transitions in the converter. Typical rise times of 1-5 ns can generate energy in the 70-350 MHz region. Both of these sources of noise must be adequately filtered in order to prevent it from interfering with the operation of the converter – degrading performance. This may require use of a multi-stage LC filters to reduce ripple and attenuate noise. To maintain DC regulation, the switching power supplies control loop can be closed around both stages of the output filter. This requires a lower loop crossover frequency to maintain stability. The load characteristic an ADC presents to the power supply is essentially DC proportional to the clock frequency. Because the load is constant, the transient response of the switching regulator is relatively unimportant and thus a low loop crossover is acceptable in this case. External compensation on the regulator makes this easier.
Adequate filtering of the noise on the output power supply voltages is critical, but also the designer must ensure that magnetic or electric field coupling from the magnetic components (inductors) included in the power supply into any baluns or transformers associated with the ADCs clock or signal paths is minimized. Placing the power supply inductors on the opposite side of the PCB and distant from the critical ADC clock and input related circuits may help to reduce this coupling.
Power Supply Decoupling
High speed ADCs present a stable overall load to the power supply but do require fast current transitions at the ADC sample rate and harmonics of this frequency. Since the inductance of the board and traces limits the amount of current that can rapidly be provided from the supply, the high frequency current required by the ADC is provided by the board power supply decoupling. Both bulk power supply decoupling and local (at the ADC pins) decoupling should be employed when powering a high speed ADC. Bulk decoupling capacitors store charge to charge the planes and local decoupling caps while the local decoupling caps provide the high frequency current needed by the ADC. Effective decoupling also minimizes EMI generated on the board by limiting high frequency power supply transients to the area very close to the IC generating the transients.
In general at least one bulk decoupling cap should be provided for each ADC power rail. These bulk capacitors should be in the range of 10 uF to 22 uf and be low ESR ceramic or tantalum capacitors. For local decoupling one capacitor per power pin is the general recommendation. These local decoupling capacitors should be low ESR ceramic capacitors in the range of 0.01uF to 0.1uF and be placed as closely as possible to the ADC power pins. These capacitors should have vias to the planes very close to the ADCs supply pins. Local decoupling can also be provided by the plane to plane capacitance if the ADC is powered from tightly coupled planes on the PCB. If these planes are relatively large and separated by less than 5 mils the capacitance between the planes provide a very effective decoupling mechanism. The plane to plane capacitance works in conjunction with the local bypass capacitors to provide the high frequency current needed by the ADC.
ADC grounding is an important piece of the power supply equation. Many ADCs today utilize an LFCSP package with a ground slug on the bottom of the package. This slug is utilized for dissipating heat from the part and in many cases this ground slug is the only ground connection for the part. This ground slug must be soldered to a ground pad on the board with several vias to the ground plane.
Noise on the ground of the ADC can also degrade performance. Often ground noise can occur when digital return currents flow through the area of the ADC. Designers should take measures to ensure that noisy ground currents are not flowing near the ADC. A continuous plane is normally recommended but a split plane may be required to isolate noisy ground currents.
The power supply implementation for an ADC can have a significant impact on the performance of the part. Following the guidelines suggested in this article should enable the design of effective ADC power supplies. The first place to look for power supply reference material for a particular ADC is at the evaluation board for the ADC. All Analog Devices ADCs have an evaluation board with a power supply included. Studying the architecture of the evaluation board power supply along with the decoupling and layout utilized is a great place to start an ADC power supply design.
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