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Power components

Guidelines For Supplying Power to High Speed ADCs

December 13, 2010 | Michael Cobb | 222901922
Guidelines For Supplying Power to High Speed ADCs Michael Cobb, Applications Engineer, High-speed Signal Processing Group, Analog Devices, provides background on ADC power domains and sensitivities and addresses basic guidelines for supplying power to high speed ADCs.
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In order to get maximum performance from a high speed analog to digital converter it must be supplied with clean DC power supplies. A noisy power supply can lead to lowered SNR and/or undesired spurious content in the ADCs output.

Analog and Digital Supplies


Most of todays high speed analog to digital converters have at least two supply domains, an analog supply (AVDD) and a digital and output driver supply (DRVDD). Some converters have an additional analog supply which typically should be treated like an extra AVDD supply discussed here. The analog and digital supplies on a converter are separated in order to prevent the digital switching noise (particularly the noise generated from the output drivers) from interfering with the sampling and processing of the analog sample on the analog side of the part. Depending on the signal being sampled this digital output switching noise can have significant frequency content and can easily degrade both noise and spurious performance if this noise is allowed back into the analog or clock inputs of the part or into the analog side of the chip through the power supplies.

For most high speed analog to digital converters two separate supplies are recommended for AVDD and DRVDD. These two supplies require sufficient isolation to prevent any digital switching noise on the DRVDD supply from reaching the AVDD supply of the converter. Often separate regulators are used for the AVDD and DRVDD supplies, however, if sufficient filtering between the two supplies is implemented it is usually possible to get adequate performance from one source.

ADC power supply sensitivity - PSRR


One method to determine a high speed ADCs sensitivity to power supply noise is to examine its power supply rejection by imposing a known frequency on the converters power supply rail and looking at the resulting tone appearing in the converters output spectrum. Looking at the relative power of the input signal versus the signal appearing in the spectrum determines the converters power supply rejection ratio (PSRR) at a given frequency. The plot below shows PSRR versus frequency for a typical high speed ADC. The data in this plot was taken with the part mounted on an evaluation board with bypass capacitors installed this method shows how the part responds to power supply noise in a typical application. Note that in this case the converters PSRR is much higher at low frequencies and drops significantly above about 10MHz.

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