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Leverage latest power devices to improve data-center efficiency

Worldwide in 2005 alone, more than $7 billion was spent on powering data-center servers and the infrastructure supporting them, requiring the equivalent capacity of fourteen 1000 MW power generating facilities [1]. While data centers are migrating to low-cost clean energy from hydroelectric sources in Oregon and Washington [2], that does not reduce the waste associated with power conversion and conditioning, distribution, and environmental control including air conditioning.

 

In fact, in a typical data center, less than half of the power consumption goes into the computing function. Consequently, data-center operators are looking at every opportunity to improve power conversion and distribution efficiency, including eliminating the number of conversion stages through the distribution of high voltage direct-current sources [3].

This feature provides an update on the great strides have been made during the last decade in the development of power semiconductor devices and products to help reduce wasted energy through improved efficiency at every stage of the power delivery system. 

In the conventional conversion and distribution process, multiple conversion stages occur. In the U.S. the electric grid distributes ac power to local communities at 13,800 volts that is eventually stepped-down to 480 Vac using transformers that do not contribute significantly to energy loss. An uninterruptible power supply (UPS) is required to ensure that the data center does not fail when a power outage occurs. Commonly, a double-conversion on-line UPS that continuously regenerates a new clean sine wave output from the rectified AC main or the battery ensures no switch over interruption and provides conditioned 208Vac to the data center through a power distribution unit. This stage of the power conditioning may be at best only 70 percent efficient [3].

At the server rack the 208-Vac power is converted to 12- or 48-Vdc and subsequently stepped down to the bus voltages required for the processor and associated components like disk drives, and memory. A switched-mode topology converts the incoming AC power to regulated DC for distribution to the server main boards and peripheral components. Both of these conversion stages, the double-conversion UPS and switched-mode ac/dc converter benefit from high-performance semiconductor components like IGBTs and super-junction power MOSFETs for rectification, battery charging, and dc/ac inverting. Present embodiments of these advanced high-voltage semiconductor components have made great strides in recent years, enabling improved performance and higher efficiency in the UPS and air-conditioning functions in the data center.

Fig.1: Power conversion stages in a typical data center. The proper application of advanced high- and low-power semiconductors can greatly improve efficiency at every stage.

Once the dc voltage is applied to the server board additional dc/dc conversions are required to provide specific regulated power to the processor, memory, and other components. At full power, the processor may use in excess of 60W. At 90 percent efficiency the voltage regulator (VR) wastes 6 W providing power to the processor. A fully populated server rack with two processors per boards could waste as much as 500 W just in the VR with every percent gain in efficiency resulting in 50 W of energy savings. High-performance, low-voltage MOSFETs have enabled improved efficiency for these conversion stages with lower on-state resistance for reduced conduction loss with new device structures enabling lower switching loss. In the last decade, VR efficiency has increased by more than 5 percent and increased the output current rating by 5 times [5].

Buck converters of past generations may have used a Shottky diode and 60-V-rated power MOSFET for switching and power-loop return, achieving 80-85 percent efficiency. Even though processor input voltage decreased, present power MOSFET products can achieve greater than 90 percent efficiency.

Advanced MOSFETs reduce VR power loss
Till the mid 1990's the focus of development in low-voltage power-MOSFET development was primarily the on-resistance (Rds_on) as conduction losses (I²R) were the dominant components of the total power loss. However, as the switching frequencies started to go up, along with the output currents, researchers across the world started to look at gate capacitance and gate charge more closely and the optimization of power devices now started to include both on-resistance as well as gate capacitance/charge. Figure 2 shows trends in the figure-of-merit for power MOSFETs -- normalized R_SP and R_SPQ_GD. As shown in the charts, there has been close to a 10X reduction in these features over the last 14 years.

Fig.2: Figure-of-merit trends for a 30-V power MOSFET over time. The past 14 years has seen a 10X improvement in performance.

With the continuing increase of output currents and switching frequencies, several new technologies have been developed to address the requirements of reduced power loss by reducing both on-resistance and gate charge.

First of these developments included the incorporation of a thicker oxide at the bottom of the gate trench (Figure 3). This not only helps in reducing the gate to drain capacitance, but also improves drift region resistance. It also helps to decouple the on-resistance and gate charge because now one can keep a thin gate oxide to get lower V_th and hence lower on-resistance, but at the same time, have a thicker trench bottom oxide to give the lowest C_GD.

Fig.3: Device cross-section of a power MOSFET with thick bottom oxide. The extra thickness reduces gate-to-drain capacitance, among many other key advantages.

Another concept that was originally developed for high voltage devices, but now being used for low voltage devices as well, is the use of charge balance or super-junction device structures. With the use of charge balance approach, one can obtain two-dimensional charge coupling in the drift region. This enables the use of higher doping in the drift region which results in reduced drift resistance. At Fairchild, this concept has been implemented using a fourth electrode, shield, along with a thick oxide, as shown in Figure 4.

Fig.4: Device cross-section of a power MOSFET with shield electrode.

Other parameters are now becoming more relevant like the body diode reverse recovery, internal gate resistance and the output charge of the MOSFET (Q_OSS). Low-voltage MOSFET products are now being optimized to minimize the diode reverse recovery as well as the output capacitance. The importance of these loss components rises at higher switching frequencies and higher output currents.

As a final component, the package resistance, inductance and its thermal properties also play a key role in determining the power loss, especially as the devices are becoming smaller in size and co-packaged solutions gain a foot-hold in the application. New package types are also being developed to minimize the die free package resistance, thermal resistance and package inductance.

In a DC-DC converter application, the main power loss components are the conduction loss, switching loss, body diode reverse recovery loss, and the gate drive loss. From a device point of view, this directly translates to the following parameters: on-resistance, gate-drain capacitance, gate-source capacitance, output capacitance, total gate charge, and the body diode reverse recovery charge. Depending on the output current and the switching frequency, each one of these can be a critical component and we need to minimize all of them to get a significant improvement in efficiency. While on-resistance controls the heavy load efficiency because conduction losses dominate at higher currents, the gate charge, reverse recovery charge and output capacitance control the light load efficiency. The chart below shows the relative power loss of various components at different output currents.

Fig.5: Relative contribution from various power loss components in a DC-DC converter.

The pace of development of silicon solutions for VR has not slowed but may in fact have accelerated in recent years. Efficiency gains, particularly at light load conditions are expected to advance significantly for VR solutions targeted for introduction in 2010 (Figure 6). Rated output current will increase further as efficiency rises enabling even less wasted power for future data centers.

Fig.6: Efficiency comparison between two generations of power MOSFET technology. Efficiency gains, particularly at light load conditions, are expected to advance significantly for voltage regulator solutions targeted for introduction in 2010

Reducing power loss in the ac/dc stage
Switch-mode power supplies (SMPS) are used in the first power conversion stage in the data centers, although telecom power supplies and white goods are also increasingly being designed with an active power factor correction (PFC) input stage to meet international regulatory standards such as EN61000-3-2 for reduced harmonic content. The objective of PFC is to make input current to power supply look resistive. An active PFC does this by programming the input current in such a way that this input current is in phase with input voltage and also matches the wave shape of input voltage. Historically, power-factor correction circuits have used a boost converter topology that combined a power switch (MOSFET or IGBT) and boost diode. However, with the introduction of the soft recovery diode like the Hyperfast Stealth (Fairchild), snubber circuitry may be eliminated or reduced, and the boost converter can be implemented in the hard-switched mode. When the Stealth diode or SiC Schottky diode is combined with new super-junction technology like SupreMOS, designers can obtain lower conduction and lower switching losses, simplified gate drive and reduced EMI.

Traditionally the ac source is rectified into a large capacitor filter and current is drawn from the source in narrow, high-amplitude pulses. This rectifier filter stage formed the front end of the SMPS. The high-amplitude current pulses produce harmonics that can cause severe interference with other equipment and reduce the maximum power that can be drawn. Distorted line voltage causes overheating of capacitors, dielectric stress and over-voltage in motor-winding insulation. Distorted line current increases distribution losses and reduces available power. Power factor correction not only ensures compliance with regulatory specifications and eliminates above failures, it also improves device conversion efficiency by increasing the maximum power that can be drawn from the source.

Most high- power active PFC designs for the ac/dc stage incorporate a continuous current mode (CCM) boost converter topology because of its simplicity and wide ac input voltage range. Another PFC operating mode, boundary conduction mode (BCM), is used at low power levels. The CCM boost converter, shown in Figure 7, operates the boost diode Db and switching device Qb in the hard-switched mode. The drawback to hard switching is that the diode reverse recovery characteristics increase the switching device's turn-on losses and the generated EMI.

The diode's reverse recovery characteristics determine how it transitions from the forward conducting state to the reverse voltage blocking state. If the return of the reverse recovery current from IRRM to zero is too abrupt or "snappy," voltage spikes and severe EMI are generated. To soften this response, circuit designers have either slowed down the switch turn on di/dt and/or added snubber circuits. With prior diode technology, the designer was limited to having either a soft or fast diode. The large IRRM value of previous soft diode technology generated high turn-on loss during the diode trr recovery period. At the same time, slowing down the switch turn-on rate increases the switch turn-on loss. Adding snubber circuitry adds to circuit cost and complexity and reduces circuit reliability. Besides, the snubber circuits often involve complex energy recovery schemes since the basic RC approach results in high power dissipation in the snubber resistor. To overcome this problem, a Stealth II diode can be used to also reduce turn-on loss.

MOSFET Rds_on contributes to the conduction loss. To reduce this loss and improve the efficiency, super-junction technology provides a a superior solution. This technology can have extremely low Rds_on which helps to reduce conduction loss. In addition, the super-junction device can be extremely fast, giving low turn-off loss. New technologies like SuperMOS and Stealth-II diode enable the highest efficiency for soft switched PFCs.

Fig.7: The continuous current boost PFC converter operates the boost diode Db and switching device Qb in the hard-switched mode. The drawback to hard switching is that the diode reverse-recovery characteristics increase the switching device's turn-on losses and the generated EMI.

Bibliography:
[1] J. Koomy "Estimating the total Power Consumption by Servers in the U.S. and the World."

[2] Retrieved 8-5-2009

[3] A. Pratt, T. Aldridge, P. Kumar, "Evaluation of 400V DC Distribution in Telco and Data Centers to Improve Energy Efficiency," INTELEC, 2007

[4] Retrieved 8-11-2009 M. K. Patterson, A. Pratt, P. Kumar, "From UPS to Silicon an end-to-end evaluation of Data Center Efficiency."

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