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Low-power 16-Bit ADCs reduce power consumption in radar and lidar applications

November 29, 2010 | Christoph Hammerschmidt | 222901858
For lower power consumption in a broad range of applications including automotive radar and lidar systems, Linear Technology Corporation has developed three families of low power 16-bit, 25Msps to 125Msps analog-to-digital converters (ADCs).

According to the vendor, the LTC2165, LTC2185 and LTC2195 families consume about 50 percent less power than competing products. The LTC2165 and LTC2185 products are single- and two-channel simultaneous sampling parallel ADCs, respectively, offering a choice of full-rate CMOS, or double data rate (DDR) CMOS/LVDS digital outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output termination. The LTC2195 family includes two-channel, simultaneous sampling ADCs with serial LVDS outputs.

Each ADC family offers a choice of pin-compatible converters, sampling from 25Msps up to 125Msps and optimized for the lowest power dissipation at the rated speed. They include popular features as Linear Technology's digital output randomizer and alternate bit polarity (ABP) mode that minimize digital feedback. These low power 16-bit ADCs enable designers to upgrade performance while maintaining portability in such applications as handheld test and instrumentation, radar/lidar, portable medical imaging, PET/SPECT scanners, smart antenna systems and a variety of low-power communication systems.

The dual LTC2185/LTC2195 and single LTC2165 consume 185mW/channel at 125Msps and offer signal to noise ratio (SNR) performance of 76.8dB and SFDR of 90dB at baseband. Pin-compatible speed grade options include 25Msps, 40Msps, 65Msps, 80Msps and 105Msps with approximate power dissipation of just 1.5mW/Msps per channel. Further power savings can be achieved by placing the devices in standby (20mW) or shutdown (1mW). Analog full power bandwidth of 550MHz and ultralow jitter of 0.07psRMS allows undersampling of IF frequencies with excellent noise performance.

Available in QFN packages, designers can benefit from the choice of interfaces that minimize pin count and ease routing to FPGAs. Parts in these families are scheduled for release now through February 2011, with demonstration boards and samples immediately available. Pricing starts at $60.00 each for the single 125Msps device in 1,000-piece quantities. More information can be found at: www.linear.com/HSADC.










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