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Power management

Power Tip 46: Time your synchronous-buck FETs properly

April 20, 2012 | Robert Kollman | 222904481
Power Tip 46: Time your synchronous-buck FETs properly In this Power Tip Robert Kollman of Texas Instruments investigates the importance of timing between the high-side and low-side FET gate drives in a synchronous buck regulator. Timing optimization is becoming increasingly important as engineers strive to eke out the best possible efficiency in their power supply.
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(Editor's note: Power Tips is an ongoing series; to see a linked list of all entries from #1 to the latest one, click here.)

There are two transitions during the switching period: the turn-on of the low-side switch, and the turn on of the highside switch. The low-side turn-on switch is critical because the transition is almost lossless, or a free ride. After the high-side switch turns off, the inductor current drives the switch-node voltage losslessly to ground. The best time to turn on the low-side switch is at the end of transition.

It is not critical if the body diode conducts a short time before the low side turns on, as it does not lead to reverse recovery loss. Any excess carriers in the junction dissipate before the next switching transition.

However, there is excess conduction loss, if the current remains in the body diode for too long. Timing the high-side FET turn-on is the most important transition. An early turn-on results in shoot-through losses due to cross-conduction with the low-side FET. A late turn-on leads to additional conduction loss and injects excess carriers in the low-side FET body diode, which must be recovered. In either case, efficiency degrades.

To characterize efficiency as a function of timing between drive signals, I constructed power supplies with adjustable delays on the driver signals. I then evaluated efficiency versus delay times. Figures 1A, 1B, and 1C show the results.

Figure 1A shows when the high-side FET is turned on before the low-side FET is fully off. An extended Miller region is apparent in the low-side gate drive where the low-side and high-side FETs are both on simultaneously, causing shoot-through current in the power stage. When the low-side FET finally turns off, there is additional voltage overshoot on the switch node.

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