Speaking at TSMC's annual technology symposium here, Shang-yi Chiang, executive vice president and co-chief operating officer at TSMC, said the firm might also offer an 18- or 16-nm process node after 20-nm if lithography technology is not available to make 14-nm devices cost effectively.

Chiang said the TSMC initially planned to offer two 20-nm processes, presumably a high performance process and a low-power process. Both processes would have featured high-k metal gate (HKMG) technology.

But, after some development, TSMC determined that there was not a noticeable performance difference between the two 20-nm processes, Chiang said. Because 20-nm linewidths are so small, approaching fundamental physical limits, there isn't much room for tweaking design rules to specify different gate lengths and other requirements, Chiang said.

TSMC offers four processes at the 28-nm node: a high performance process, a low power process, another low power process with HKMG and a high performance process geared for mobile applications.

TSMC expects its 20-nm HKMG process to be in production next year. In 2015, TSMC wants to commence production at the 14-nm node, adding FinFET 3-D transistors.

But the semiconductor industry is waiting on extreme ultraviolet (EUV) lithography, which has been delayed several times. To date, no power source has been developed to provide the power and stability necessary to enable volume production at sufficient throughput. Lithography tool vendor ASML Holding NV is working with several power source developers on the technology and has pledged to make available tools with sufficient throughput later this year for commercial chip production in 2013 and 2014.

But many in the industry remain skeptical that EUV will be available in time to support the aggressive roadmaps of TSMC and other leading-edge chip manufacturers. Chiang also noted that lithographers have made a great deal of progress on the 193-nm immersion lithography to the point where it could be a commercially viable alternative at 14-nm. However, Chiang said, 193-nm immersion might require triple-patterning on some layers and double patterning on many layers in order to achieve adequate image fidelity, which would make it too costly for volume production.

Chiang said TSMC is "thinking very carefully" about whether to offer an 18- or 16-nm process. "If we choose this node, we will have to offer it to customers for 10 years," Chiang said.