What really limits MOSFET performance: silicon, package, driver or circuit board? (Part 2 of 2)
(Part 1 is available here)
Minimizing Package Parasitics
Simple mathematical analysis shows that the best answer to address this problem is to select a CR ratio QGD/QGS1 that is less than 1. Other factors to consider for preventing C dv/dt induced turn-on include low driver-sinking impedance (<1 ), a FET design with intrinsically low RG, an externally-applied G-S capacitor and Q2 packages that minimize parasitics and voltage ringing.
The on-resistance RDS(on) of the sync MOSFET Q2, and its packaging, are equally important factors in curbing C dv/dt turn-on. In fact, in last several years, MOSFET suppliers have made dramatic improvements in packages to keep on-resistance very low and parasitics minimal. For instance, take the 7-pin D2PAK. By comparison, it offers 0.4 m less RDS(on) than a comparable standard D2PAK, while substantially improving current-handling capability for the same drain-source voltage VDS. A good representative in a 7-pin D2PAK is IRFS3004-7PPBF, a 40-V rated MOSFET with 1.4 m RDS(on) and 240 A drain current (ID) capability. The same silicon in a conventional D2PAK version offers 1.8 m RDS(on) with ID rated for195 A.
Other improved power packages include power quad flat-pack no-lead (PQFN) and DirectFET.. There are many variants of the PQFN packaging style. However, unlike others, DirectFET completely eliminates wire bonds and leadframe to give the least package resistance and parasitic inductance as shown in Figure 4.
Measured die free-package resistance and parasitic inductance versus frequency for different types of MOSFET packages is plotted in Figures 5 and 6.
It is seen from these illustrations that DirectFET packages contribute negligible resistance and inductance versus frequency, when compared to other packaging formats like DPAK, D2PAK, SO8 and micro leadframe package (MLP). Additionally, the variation in DirecFETs parasitic values is minimal with frequency, as compared to leaded packages, because package-contributed resistance and inductance has been cut to a bare minimum.
With recent improvements in DirecFET material and construction, the package resistance has been reduced to 0.15 m and parasitic inductance to less than 0.1 nH. The only other package that comes close to DirectFET in terms of package resistance and inductance is MLP, a variation of PQFN.
To put the above discussion into perspective and better understand the contribution of C dv/dt loss to the overall circuit loss, lets take two MOSFETs with parameters as shown in Table 1.
Device #1 offers high RDS(on) and low CR value, while device #2 is a low RDS(on) transistor with high CR ratio. These two devices are used in the sync FET socket of the synchronous buck converter with the same Q1 MOSFET and 1-MHz switching frequency. The input voltage is 14 V and output is 1.3 V.
The measured losses for the two different sync FETs are illustrated in Figure 7.
As shown in this figure, device #1 shows lower loss as compared to device #2 over a wide range of output load. In fact, at 10 A load, device #1 offers 0.72 W lower loss than device #2. Overall, the device #2 is showing about 18% higher loss than #1, which is contributed by the C dv/dt turn-on loss. The secret is that device #1 has lower Qgd and CR ratio and, therefore, it suffers less or no C dv/dt loss. Since C dv/dt loss is not a strong function of load current, a similar amount of power loss delta stays at light load.
Layout is another factor that can undermine the performance of a good MOSFET in a power supply design. For instance, a poor board layout can add more parasitics to the power-supply circuit, which in turn can increase switching and conduction losses of the design. In addition, it can raise the EMI noise level and cause a good design to deliver less-than-expected performance.
To minimize the impact of board layout, the designer must ensure that the input loop area is made physically as small as possible, by placing the driver and MOSFETs back-to-back when possible, as shown in Figure 8.
The right side of this picture has a small ceramic bypassing capacitor underneath the FET, and uses vias to form a very small input loop. Hence, place bypass capacitors next to the driver, as well as place input ceramic capacitor CIN close to the high-side MOSFET. Here, the control-loop FET has a higher priority than sync FET.
When paralleling FETs, make sure the gate loop impedances are matched. Plus, the layout must use separate analog-ground and power-ground planes so that the high current path is localized in a separate loop that does not interfere with the sensitive analog circuit. These two grounds then must be connected together on the PCB layout at a single point. In addition, the design must use multiple vias to connect FETs to input pin Vin or ground planes. Any unused area on the board must be filled with copper.
In summary, package impedance, PCB layout, interconnect parasitic, and switching speed are all critical factors influencing a MOSFETs performance in a power-supply circuit. Hence, to get the best conversion efficiency with high power density, the MOSFET must be designed in context with packaging and board layout, including interconnect and impedances, along with switching speed.
He has authored and presented more than 60 tutorials and papers at various international conferences. In addition he has presented power electronic short courses and lectures for the University of Minnesota, UW Madison, and Purdue University. Mr. Persson holds 12 US and foreign patents, and is a recipient of the IEEE Third Millennium Medal.
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