(Part 1 is available here)

Minimizing Package Parasitics

Simple mathematical analysis shows that the best answer to address this problem is to  select a CR ratio Q_GD/Q_GS1 that is less than 1. Other factors to consider for preventing C dv/dt induced turn-on include low driver-sinking impedance (<1 Ώ), a FET design with intrinsically low R_G, an externally-applied G-S capacitor and Q2 packages that minimize parasitics and voltage ringing.

The on-resistance R_DS(on) of the sync MOSFET Q2, and its packaging, are equally important factors in curbing C dv/dt turn-on. In fact, in last several years, MOSFET suppliers have made dramatic improvements in packages to keep on-resistance very low and parasitics minimal. For instance, take  the 7-pin D2PAK. By comparison, it offers 0.4 mΩ less R_DS(on) than a comparable standard D2PAK, while substantially improving current-handling capability for the same drain-source voltage V_DS. A good representative in a 7-pin D2PAK is IRFS3004-7PPBF, a 40-V rated MOSFET with 1.4 mΩ R_DS(on) and 240 A drain current (I_D) capability. The same silicon in a conventional D2PAK version offers 1.8 mΩ R_DS(on) with I_D rated for 195 A.

Other improved power packages include power quad flat-pack no-lead (PQFN) and DirectFET.. There are many variants of the PQFN packaging style. However, unlike others, DirectFET completely eliminates wire bonds and leadframe to give the least package resistance and parasitic inductance as shown in Figure 4.

Figure 4: DirectFET minimizes package resistance and parasitic inductance
(Click on image to enlarge)

Measured die free-package resistance and parasitic inductance versus frequency for different types of MOSFET packages is plotted in Figures 5 and 6.

Figure 5: Package resistance and parasitic inductance vs frequency for various packages
(Click on image to enlarge)

Figure 6: Package resistance and parasitic inductance vs frequency
(Click on image to enlarge)

It is seen from these illustrations that DirectFET packages contribute negligible resistance and inductance versus frequency, when compared to other packaging formats like DPAK, D2PAK, SO8 and micro leadframe package (MLP). Additionally, the variation in DirecFET’s parasitic values is minimal with frequency, as compared to leaded packages, because package-contributed resistance and inductance has been cut to a bare minimum.

With recent improvements in DirecFET material and construction, the package resistance has been reduced to 0.15 mΩ and parasitic inductance to less than 0.1 nH. The only other package that comes close to DirectFET  in terms of package resistance and inductance is MLP, a variation of PQFN.

Maximizing Performance

To put the above discussion into perspective and better understand the contribution of C dv/dt loss to the overall circuit loss, let’s take two MOSFETs with parameters as shown in Table 1.

Table 1: Parameters of two representative MOSFETs
(Click on image to enlarge)

Device #1 offers high R_DS(on) and low CR value, while device #2 is a low R_DS(on) transistor with high CR ratio. These two devices are used in the sync FET socket of the synchronous buck converter with the same Q1 MOSFET and 1-MHz switching frequency. The input voltage is 14 V and output is 1.3 V.

The measured losses for the two different sync FETs are illustrated in Figure 7.

Figure 7: Losses for two different types of sync FETs
(Click on image to enlarge)