Discrete 1200V MOSFET claims industry’s lowest Figure-of-Merit

February 24, 2017 // By Nick Flaherty
Cree-subsidiary Wolfspeed has launched a third generation 1200V silicon carbide MOSFET in low inductance packaging that it claims has the industry’s lowest figure of merit for a discrete device.

The C3M0075120K simplifies designs and enables an increase in frequency while maintaining efficiency, lowering system cost, reducing circuit EMI and enabling 99% efficiency levels in three-phase power factor correction circuits. This enables designers of applications such as telecom power supplies, elevators, grid-tied storage, on and offboard EV charging, as well as factory automation to increase switching frequency while maintaining efficiency, decreasing system size and bill of materials.

“We are very encouraged about the new SiC products being introduced in new innovative discrete packaging,” said Kurt Goepfrich, a Siemens hardware architect. “These new package options, such as the surface-mount 7L D2PAK, allow us to explore new topologies not possible with existing products available on the market today.”

Wolfspeed has released this device in a 4L TO-247 through hole package and plans to release it in a surface mount 7L D2PAK.

“SiC MOSFETs have proven to be beneficial for many high-power applications connected to a battery simply due to the improved efficiency,” said John Palmour, Wolfspeed’s CTO. “In the case where power is bidirectional, such as grid-connected AC-DC, the potential cost savings are significantly increased due to the reduction in the size of the input filter.”

The device uses Wolfspeed’s third generation C3M planar MOSFET technology that gives a low on-resistance of 75mΩ with a low gate charge of 51nC, making it ideally suited for three-phase, bridgeless PFC topologies as well as AC-AC converters and chargers.

The 4L TO247 package delivers a 3x reduction in total switching losses compared to a conventional TO-247-3 package.

The 7L D2PAK surface-mount package, specifically designed for high-voltage MOSFETs, almost eliminates the source inductance found in other packages and has a footprint half that of the D3PAK. This is made possible by the small die size and high-blocking capability of the C3M planar MOS technology.

Designers can reduce component-count by moving from silicon-based, three-level topologies to simpler two-level topologies made possible by the improved switching performance. These higher