Signal integrity tool update speeds PCB power integrity signoff

January 26, 2017 // By Graham Prophet
The latest version of Cadence’s Sigrity tool has added several features specifically designed to speed up PCB power and signal integrity signoff. Signal analysis capability is also included to handle increasingly complex high-speed interconnect designs, including PCIe 4.0.

Among the features included in the newest version of the Sigrity portfolio are the Allegro PowerTree topology viewer and editor, which enable designers to assess power delivery decisions early in the design cycle. The latest release of Sigrity also includes a PCI Express (PCIe) 4.0 compliance kit for checking signal integrity compliance with the latest PCIe specification when it is certified later in 2017.

Determining the path for power delivery early in the design cycle is, Cadence asserts, critical to PCB design teams. The PowerTree user interface allows for a power topology to be viewed for quick and accurate determination of the best path for power delivery. The technology also allows for easy editing as designs change. The information stored in the PowerTree environment is then used later in the design cycle to provide automated setup of post-route power integrity analysis for faster closure. Also included in the Sigrity 2017 release is library management for power integrity models through the analysis model manager.

Sigrity 2017 also helps designers incorporate the latest PCIe technology for high-speed interconnect as they work to ensure signal integrity. It includes a compliance kit for PCIe 4.0 interfaces in the Sigrity SystemSI Serial Link Analysis tool to automatically qualify signal quality standards instead of manually checking and measuring against standards documents.

Cadence Design Systems; www.cadence.com/go/sigrity2017