The LTC2145 family includes two-channel simultaneous sampling, parallel output ADCs, offering a choice of full-rate CMOS, or double data rate (DDR) CMOS or DDR LVDS digital outputs with programmable digital output timing, programmable LVDS output current and optional LVDS output termination.
At 25 Msps the 14-bit and 12-bit versions of the LTC2140 consume just 24 mW per channel, while the 125 Msps LTC2145 consumes 95 mW per channel. While claiming the lowest power dissipation, AC performance has not been compromised.
At 14-bits, these devices achieve over 73.2 dB SNR performance with 90 dB of SFDR at baseband. At 12-bits, the SNR performance is better than 70.6 dB. This ADC family offers a pin-compatible upgrade path to the ultralow power LTC2185 16-bit ADC family to provide a 3 dB performance upgrade while maintaining portability in such applications as handheld test and instrumentation, radar/LIDAR, medical imaging, PET/SPECT scanners, military radios, smart antenna systems and a range of low-power communication systems.
Pin-compatible speed grade options include 25 Msps (24 mW/ch), 40 Msps (33 mW/ch), 65 Msps (46 mW/ch), 80 Msps (55 mW/ch), 105 Msps (75 mW/ch) and 125 Msps (95 mW/ch). Additional power savings can be achieved by placing the devices in standby (16 mW) or shutdown (1 mW). Analog full power bandwidth of 750 MHz and ultralow jitter of 0.08 psRMS allows undersampling of IF frequencies with excellent noise performance. These devices incorporate Linear Technology's digital output randomizer and alternate bit polarity (ABP) mode feature for reduced digital feedback.
Availability and Pricing
Available in compact 9 mm x 9 mm QFN packages, designers can benefit from the flexible choice of interfaces that minimize pin count and ease routing to FPGAs. These ADCs will be available in production quantities beginning in May through June 2011. Pricing starts at $10.95 each for the dual 12-bit 25 Msps devices in 1,000-piece quantities.
More information about the LTC2145 ADC family at www.linear.com/HSADC